To support a requirement of multiple types of rates for an Ethernet interface, a transmit MAC (English: transmit media access controller, transmit MAC for short) in an existing high-speed Ethernet interface converts a packet flow into a data block flow, and distributes a data block in the data block flow to N virtual lanes (English: virtual lane, VL for short). For example, the multiple types of rates may be two types of rates. The two types of rates may respectively correspond to M0 bitstreams and M1 bitstreams. A value of N is a minimum common multiple of M0 and M1. After the data block flow is distributed to the N virtual lanes, an alignment marker (English: alignment marker, AM for short) needs to be inserted into each data block flow, and an AM of each lane includes an identifier of a virtual lane. After receiving the data block flow from the N virtual lanes, a transmit PMA (English: transmit physical medium attachment, transmit PMA for short) multiplexes the received data block flow into M bitstreams in a bit interleaved manner. After receiving the M bitstreams, a receive PMA (English: receive PMA) demultiplexes the bitstreams into N data block flows in a bit interleaved manner. A receive PCS (English: receive physical coding sublayer, receive PCS for short) performs alignment and reordering according to an alignment marker in the N data block flows. The PMA performs multiplexing and demultiplexing from N to M in a bit interleaved manner, and the N data block flows are out-of-order in a receive MAC (English: receive media access controller, receive MAC for short). That is, when a data block flow in the transmit MAC arrives at the receive MAC, the data block flow may exist in any data block flow of the N data block flows in the receive MAC. The receive PCS needs to perform reordering on the N data block flows to map data blocks in the N data block flows to the N virtual lanes. To implement the foregoing mapping, a full mesh (English: full mesh) needs to be established between the N virtual lanes by using a circuit, and the receive PCS needs to include N×(N−1) connections. In the foregoing technical solution, many circuit resources are occupied.
For example, to implement an Ethernet interface of 100 gigabits per second (gigabit per second, Gps for short), a 4×25 Gps solution and a 10×10 Gps solution are proposed in the industry. To support both the 4×25 Gps solution and the 10×10 Gps solution, the transmit MAC needs to convert a packet flow into a data block flow, and distribute the data block flow to 20 virtual lanes, where 20 is a minimum common multiple of 4 and 10.
After receiving a 4×25 Gps bitstream or a 10×10 Gps bitstream, the receive PMA demultiplexes the 4×25 Gps bitstream or the 10×10 Gps bitstream into 20 data block flows. The receive PCS performs reordering on data blocks in the 20 data block flows according to an identifier of a virtual lane in a data block. When performing the reordering, the receive PCS needs to map the data blocks in the 20 data block flows to the 20 virtual lanes. To implement the foregoing mapping, a full mesh needs to be established between the 20 virtual lanes by using a circuit (such as a logic circuit). Therefore, the receive PCS needs to include 20×19 connections.